Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Simulation of Semiconductor Devices and Circuits at High Frequencies

Due to the rapid progress in semiconductor technology, device sizes could be continually decreased during the last decades. This reduction allows for a higher package density which in turn increases the demands on modern simulation tools. This article covers some of the recent advances on the fields of device, circuit, and interconnect simulation which are fundamental requirements for accurate simulation of state-of-the-art circuits

Extended papers selected from ESSDERC 2015

This special issue of Solid State Electronics includes 28 papers which have been carefully selected from the best presentations given at the 45th European Solid-State Device Research Conference (ESSDERC 2015) held from September 14–18, 2015 in Graz, Austria. These papers cover a wide range of topics related to the research on solid-state devices. These topics are used also to organize the conference submissions and presentations into 7 tracks: CMOS Processes, Devices and Integration; Opto-, Power- and Microwave Devices; Modeling & Simulation; Characterization, Reliability & Yield; Advanced & Emerging Memories; MEMS, Sensors & Display Technologies; Emerging Non-CMOS Devices & Technologies

Performance Portability Study of Linear Algebra Kernels in OpenCL

The performance portability of OpenCL kernel implementations for common memory bandwidth limited linear algebra operations across different hardware generations of the same vendor as well as across vendors is studied. Certain combinations of kernel implementations and work sizes are found to exhibit good performance across compute kernels, hardware generations, and, to a lesser degree, vendors. As a consequence, it is demonstrated that the optimization of a single kernel is often sufficient to obtain good performance for a large class of more complicated operations.Comment: 11 pages, 8 figures, 2 tables, International Workshop on OpenCL 201

Modeling of negative bias temperature instability, Journal of Telecommunications and Information Technology, 2007, nr 2

Negative bias temperature instability is regarded as one of the most important reliability concerns of highly scaled PMOS transistors. As a consequence of the continuous downscaling of semiconductor devices this issue has become even more important over the last couple of years due to the high electric fields in the oxide and the routine incorporation of nitrogen. During negative bias temperature stress a shift in important parameters of PMOS transistors, such as the threshold voltage, subthreshold slope, and mobility is observed. Modeling efforts date back to the reaction-diffusion model proposed by Jeppson and Svensson thirty years ago which has been continuously refined since then. Although the reaction-diffusion model is able to explain many experimentally observed characteristics, some microscopic details are still not well understood. Recently, various alternative explanations have been put forward, some of them extending, some of them contradicting the standard reaction-diffusion model. We review these explanations with a special focus on modeling issues

On the Thermal Activation of Negative Bias Temperature Instability

The temperature dependence of negative bias temperature instability (NBTI) is investigated on 2.0nm SiO2 devices from temperatures ranging from 300K down to 6K with a measurement window of ~12ms to 100s. Results indicate that classic NBTI degradation is observed down to ~200K and rarely observed at temperatures below 140K in the experimental window. Since experimental results show the charge trapping component contributing to NBTI is thermally activated, the results cannot be explained with the conventionally employed elastic tunneling theory. A new mechanism is observed at temperatures below 200K where device performance during stress conditions improves rather than degrades with time, which is opposite to the classical NBTI phenomenon

MODELING OF HOT-CARRIER DEGRADATION BASED ON THOROUGH CARRIER TRANSPORT TREATMENT

We present and validate a physics-basedmodel for hot-carrier degradation. The model is based on a thorough carrier transport treatment by means of an exact solution of the Boltzmann transport equation. Such important ingredients relevant for hot-carrier degradation as the competing mechanisms of bond dissociation, electron-electron scattering, the activation energy reduction due to the interaction of the dipole moment of the bond with the electric field as well as statistical fluctuations of this energy are incorporated in our approach. The model is validated in order to represent the linear drain current change in three different devices subjected to hot-carrier stress under different conditions. The main demand is that the model has to use a unique set of parameters. We analyze the importance of all the model ingredients, especially the role of electron-electron scattering. We check the idea that the channel/gate length ofthe device alone is not enough to judge whether electron-electron scattering is important or not and instead a combination of the device topology and stress conditions needs to be used

Analysis of Worst-Case Hot-Carrier Conditions for n-type MOSFET

Abstract-We analyze the worst-case conditions of hot-carrier induced degradation with our model which is based on the evaluation of the carrier distribution function along the Si/ SiO2 interface, i.e. thorough consideration of carrier transport. The distribution function obtained by means of a full-band Monte-Carlo device simulator is used to calculate the acceleration integral, which controls how effectively the carriers are breaking Si-H bonds. Therefore, we analyze these worst-case conditions using this integral as a criterion. We compare the numerical picture with the experimental one and conclude that the model fits the experimental data rather accurately and confirm that these conditions correspond to the relation Vgs = 0.4Vds between gate and drain voltages. The simplified treatment of carrier transport using the non-Maxwellian but still analytical distribution function is also discussed. A discrepancy between experimental results and simulations, which occurred while employing this simplified approach, is shown and explained